Staff Engineer- Dft

Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware EngineeringQualcomm Overview:
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

General Summary

Interface with design team to ensure DFT design rules and coverages are met.

Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.

MBIST verification (including repair), test pattern generation through Mentor tool.

ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.

Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.

Responsible for supporting post silicon debug effort, issue resolution.

Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.

Developing, enhancing and maintaining scripts as necessary

Minimum of 6-8 years’ experience in ASIC/DFT – simulation and Silicon validation

Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement

In depth knowledge and hands-on experience in ATPG - coverage analysis.

In depth knowledge of Memory verification, repair and failure root-cause analysis.

Experience With Any Of These Tools Is Required

ATPG - TestKompress

MBIST - Mentor ETVerify

Simulation - VCS (preferred), modelsim.

Expertise in scripting languages such as Perl, shell, etc. is an added advantage

Ability to work in an international team, dynamic environment with good communication skills

Ability to learn and adapt to new tools, methodologies.

Ability to do multi-tasking & work on several high priority designs in parallel.

BE with minimum of 10 years/ME with minimum of 6-8 years of experience in DFT/ATPG/BIST

• Interface with design team to ensure DFT design rules and coverages are met.
• Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques.
• MBIST verification (including repair), test pattern generation through Mentor tool.
• ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
• Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
• Responsible for supporting post silicon debug effort, issue resolution.
• Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE.
• Developing, enhancing and maintaining scripts as necessary
• Minimum of 6-8 years’ experience in ASIC/DFT – simulation and Silicon validation
• Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement
• In depth knowledge and hands-on experience in ATPG - coverage analysis.
• In depth knowledge of Memory verification, repair and failure root-cause analysis.
• Experience with any of these tools is required
  
  • ATPG - TestKompress
  • MBIST - Mentor ETVerify
  • Simulation - VCS (preferred), modelsim.
    
    
• Expertise in scripting languages such as Perl, shell, etc. is an added advantage
• Ability to work in an international team, dynamic environment with good communication skills
• Ability to learn and adapt to new tools, methodologies.
• Ability to do multi-tasking & work on several high priority designs in parallel.
• BE with minimum of 10 years/ME with minimum of 6-8 years of experience in DFT/ATPG/BIST
  
  
  
  

Education

Minimum Qualifications

Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems

Work Experiences

5+ years Hardware Engineering experience or related work experience.

Skills

Certifications:

Education

Preferred Qualifications

Masters - Computer Science, Masters - Engineering, Masters - Information Systems

Work Experiences

1+ years in a technical leadership role with or without direct reports. ,2+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. ,2+ years experience utilizing schematic capture and circuit simulation software. ,2+ years experience with circuit design (e.g., digital, analog, RF). ,8+ years Hardware Engineering experience or related work experience.

Skills

Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

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