Design Verification Manager (dsp Processor)

Job details

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Job description

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Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group
Hardware Engineering

Job Overview:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

GENERAL SUMMARY Job Title : Design Verification Manager (CPU)
Division : Qualcomm Technologies, Inc
Job Area : Engineering – Hardware
Location : India – Bangalore
Education: Bachelors or Master’s degree in EE/CS

Job Summary:

• This position is for design verification Manager role of complex Qualcomm propriety Hexagon DSP IP
• DSP design team is responsible for delivering high-performance DSP cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space

Job Responsibilities:

• People management responsibility for entire DV team of ~25 people
• Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, post silicon and back-end teams
• Implement and improve System Verilog Testbench Architecture
• Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency
• Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals
• Hand-on simulations and debug
• Complete all required verification activities at IP level and insure high quality commercial success of our products
• Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis
• Responsible gate level simulation bring up, gate level verification with timing simulations
• Responsible for power aware RTL and gate level simulation

Skillset/Experience:

• 15-20 years’ experience in processor/ASIC design verification
• Solid background and understanding of Digital Design, Processor Architecture and Processor Verification
• Expertise in System Verilog Testbench Architecture and implementation
• Experience in VERA/System Verilog, simulators from Synopsys/Mentor/Cadence
• Scripting/Automation Skills — Perl, Python, Shell, Make file TCI
• Solid analytic and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts
• Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL is preferred
• Experience in AMBA, AHB, AXI, JTAG and debug protocols
• Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware
• Experience is verification of Processor subsystems (ARM/DSP) is preferred
• Experience in creating validation suite and building automation
• Should have excellent inter-personal and communication skills
• Exposure to silicon bring up, silicon testing , bench and application testing is a definite plus

Minimum Qualifications

Education: Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems

Work Experiences: 15+ years ASIC design, verification, or related work experience

Certifications:

Skills:

Preferred Qualifications

Education:

Work Experiences: 2+ years experience with circuit design (e.g., digital, analog, RF). ,2+ years experience utilizing schematic capture and circuit simulation software. ,2+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. ,1+ years in a technical leadership role with or without direct reports. ,6+ years Hardware Engineering experience or related work experience.

Certifications:

Skills: Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to

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